The present invention generally relates to delay elements within integrated or logic circuits and more particularly to area and power efficient delay elements.
Delay elements are common in modern integrated circuits, such as programmable logic devices (PLD) and application specific integrated circuits (ASIC). One use of delay elements is to control the timing of signals, such as the timing between data signals and clock signals. For example, it is sometimes favorable to slow down data signals to prevent data corruption at storage elements before the appropriate data can be successfully captured. Also, it is sometimes favorable to slow down clock signals to storage elements to give data signals more time to reach those storage elements. Additionally, signals may be slowed down to reduce the skew between signal paths so as to equalize the propagation delay between different signal paths or to achieve a requested skew between the signal paths.
In order to slow down signals, there are two general approaches, which may be used in combination: using many logic or routing elements along the signal path; or using slower logic or routing elements along the signal path. The latter approach is generally favored when it is feasible because it wastes fewer elements. Delay elements are an example of these slower elements that can be efficiently used to slow down signal paths. Delay elements are often programmable so that the amount of delay they add to a signal path can be controlled. Programmability is useful because it is often important to achieve a particular range of delays rather than any delay greater than a specified value. Consequently, due to their usefulness and efficiency, programmable delay elements are common in modern PLDs, especially in input and output (10) blocks.
As delay elements occur frequently, the amount of area and energy used by the delay elements can be quite large. The area used for delay elements contributes to the manufacturing cost of a circuit, as well as to additional design costs. Thus, it would be beneficial for the delay elements to be as small as possible while potentially achieving the same level of programmability. Also, the energy used by a delay element contributes to the operating cost of a circuit, which would also preferably be minimized.
Thus, what are needed are circuits, methods, and apparatus for providing area and energy efficient delay elements.